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Published 2 years ago • Latest: 0.6.7
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The Rapid Open Hardware Development (ROHD) framework, a framework for describing and verifying hardware

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0.5.0 #

  • Added LogicArray for N-dimensional packed and unpacked (and mixed) arrays. Added LogicStructure for grouping sets of related signals together in a convenient way (https://github.com/intel/rohd/pull/375).
  • Added a ConditionalGroup which can group a collection of other Conditionals into one Conditional object.
  • Breaking: some APIs which previously returned ConditionalAssign now return a Conditional, such as the < operator for Logic.
  • Updated LogicValue.of which now accepts a dynamic input and tries its best to build what you're looking for. Added LogicValue.ofIterable to replace the old LogicValue.of.
  • Added previousValue to Logic to make testbench and modelling easier for things like clock edge sampling.
  • Breaking: Modified the way Combinational sensitivities are implemented to improve performance and prevent some types of simulation/synthesis mismatch bugs. Added Combinational.ssa as a method to safely build procedural logic. Combinational will now throw fatal exceptions in cases of "write after read" violations. (https://github.com/intel/rohd/pull/344)
  • Deprecated getReceivers, getDrivers, and getConditionals in always blocks like Combinational and Sequential in favor of simpler and more efficient APIs receivers, drivers, and conditionals.
  • Breaking: shorthand notation APIs for incr, decr, mulAssign, and divAssign have been modified.
  • Replaced IfBlock with If.block (deprecated IfBlock).
  • Replaced StateMachine with FiniteStateMachine (deprecated StateMachine).
  • Added support for multi-trigger (e.g. async reset) to abstractions like FiniteStateMachine and Pipeline. Deprecated clk on FiniteStateMachine and Pipeline.
  • Added ability to generate an FSM diagram in mermaid from a FiniteStateMachine.
  • Added PairInterface to make it easier to build and use simple Interfaces.
  • Breaking: connectIO in Interface now accepts Iterables instead of only Sets.
  • Improved numerous Exceptions throughout to provide more specific information about errors and make them easier to catch and handle.
  • Upgraded some operations to avoid generating unnecessary hardware and SystemVerilog when configured to leave a signal unchanged (e.g. getRange, swizzle, slice, etc.).
  • Added extension to generate randomized LogicValues from a Random.
  • Added replication operations to LogicValue and Logic.
  • Added equalsWithDontCare to LogicValue for comparisons where invalid bits are "don't-care".
  • Improved timestamps in generated outputs to make timezones apparent.
  • Added the flop function to construct FlipFlops in an easier way.
  • Added the cases function to construct simple Case statements in an easier way.
  • Added APIs for configuring reset and reset values in Sequential and flip flops.
  • Added APIs for adding an enable to flip flops.
  • Implemented a variety of performance enhancements for both build and simulation.
  • Added tryInput and tryOutput to Module and tryPort to Interface to more easily handle conditionally present ports by leveraging Dart's null safety by returning null if the port does not exist (instead of an exception).
  • Added gt and gte to Logic to make APIs more consistent.
  • Added clog2 to LogicValue.
  • Added neq and pow to both Logic and LogicValue.
  • Made LogicValue implement Comparable, enabling things like sorting.
  • Enabled WaveDumper to recursively create necessary directories for specified output paths.
  • Fixed a bug where ports could be created with an empty string as the name (https://github.com/intel/rohd/issues/281).
  • Fixed a bug where generated SystemVerilog for arithmetic shift-right operations would sometimes be incorrect (https://github.com/intel/rohd/issues/295).
  • Fixed a bug where SynthBuilder would not flag an error when run on a Module that hadn't yet been built (https://github.com/intel/rohd/issues/246).
  • Disallowed signals from being connected directly to themselves in a combinational loop.
  • Fixed a bug where non-synthesizable deposits on undriven signals could affect the generated output SystemVerilog by inserting a non-floating constant (https://github.com/intel/rohd/issues/254).
  • Reinstated an accidentally removed exception for when signal width mismatch occurs (https://github.com/intel/rohd/issues/311).
  • Fixed a bug where indexing a constant value could generate invalid SystemVerilog.
  • Fixed a bug where constants and values that could be interpreted as negative 64-bit values would sometimes generate a - sign in output SystemVerilog.
  • Fixed bugs so Ifs that are illegally constructed throw an Exception (https://github.com/intel/rohd/issues/382).
  • Fixed a bug where FiniteStateMachine could create an inferred latch (https://github.com/intel/rohd/pull/390).
  • Fixed an issue where Case statements with multiple matches would throw an Exception instead of driving x on the output, which could cause spurious crashes during glitch simulation (https://github.com/intel/rohd/issues/107).
  • Fixed a number of bugs related to logical, shift, math, and comparison operations related to width and sign interpretation.
  • Fixed a bug where Case and CaseZ would not use the properly edge-sampled value in Sequential blocks (https://github.com/intel/rohd/issues/348).
  • Fixed bugs where logic that is driven by floating signals would sometimes drive z instead of x on outputs (https://github.com/intel/rohd/issues/235).

0.4.2 #

0.4.1 #

0.4.0 #

0.3.2 #

  • Added the StateMachine abstraction for finite state machines.
  • Added support for the modulo % operator.
  • Added ability to register actions to be executed at the end of the simulation.
  • Modified the WaveDumper to write to the .vcd file asynchronously to improve simulation performance while waveform dumping is enabled (https://github.com/intel/rohd/issues/3)

0.3.1 #

0.3.0 #

  • Breaking: Merged LogicValue and LogicValues into one type called LogicValue.
  • Deprecation: Aligned LogicValue to Logic by renaming length to width.
  • Breaking: Logic.put no longer accepts List<LogicValue>, swizzle it together instead.
  • Deprecated Logic.valueInt and Logic.valueBigInt; instead use equivalent functions on Logic.value.
  • Deprecated bit on both LogicValue and Logic; instead just check width.
  • Added ability in LogicValue.toString to decide whether or not to include the width annotation through includeWidth argument.
  • Fixed a bug related to zero-width construction of LogicValues (https://github.com/intel/rohd/issues/90).
  • Fixed a bug where generated constants in SystemVerilog had no width, which can cause issues in some cases (e.g. swizzles) (https://github.com/intel/rohd/issues/89)
  • Added capability to convert binary strings to ints with underscore separators using bin (https://github.com/intel/rohd/issues/56).
  • Added getRange and reversed on Logic and slice on LogicValue to improve consistency.
  • Using slice in reverse-index order now reverses the order.
  • Added the ability to extend signals (e.g. zeroExtend and signExtend) on both Logic and LogicValue (https://github.com/intel/rohd/issues/101).
  • Improved flexibility of IfBlock.
  • Added withSet on LogicValue and Logic to make it easier to assign subsets of signals and values (https://github.com/intel/rohd/issues/101).
  • Fixed a bug where 0-bit signals would sometimes improperly generate 0-bit constants in generated SystemVerilog (https://github.com/intel/rohd/issues/122).
  • Added capability to reserve instance names, as well as provide and reserve definition names, for Modules and their corresponding generated outputs.

0.2.0 #

  • Updated implementation to avoid Iterable.forEach to make debug easier.
  • Added ofBool to LogicValue and LogicValues (https://github.com/intel/rohd/issues/34).
  • Breaking: updated Interface API so that getPorts returns a Map from port names to Logic signals instead of just a list, which makes it easier to work with when names are uniquified.
  • Breaking: removed setPort from Interface. Use setPorts instead.
  • Deprecated swizzle and rswizzle global functions and replaced them with extensions on Lists of certain types including Logic, LogicValue, and LogicValues (https://github.com/intel/rohd/issues/70).
  • Breaking: renamed ExternalModule to ExternalSystemVerilogModule since it is specifically for SystemVerilog.
  • Breaking: made topModuleName a required named parameter in ExternalSystemVerilogModule to reduce confusion.
  • Added simulationHasEnded bool to Simulator.
  • Updated Simulator to allow for injected actions to return Futures which will be awaited.
  • Fixed bug where Simulator warns about maximum simulation time when not appropriate.
  • Fixed a bug where ExternalSystemVerilogModule could enter infinite recursion.
  • Some improvements to SimCompare to properly check values at the end of a tick and support a wider variety of values in Vectors.
  • Fixed a bug related to Sequential signal sampling where under certain scenarios, signals would pass through instead of being flopped (https://github.com/intel/rohd/issues/79).
  • Deprecated a number of from functions and replaced them with of to more closely follow Dart conventions (https://github.com/intel/rohd/issues/72).

0.1.2 #

0.1.1 #

0.1.0 #

  • The first formally versioned release of ROHD.

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The Rapid Open Hardware Development (ROHD) framework, a framework for describing and verifying hardware

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